In D. Preslar and J. Siwinski in "An ECL/12L Frequency Synthesizer for AM/FM Radio with an Alive Zone Phase Comparator" at p. 20 of IEEE Transactions Consumer Electronics (1981), a delay circuit is incorporated in the digital phase detector to provide a fixed delay time. However, the delay circuit is hampered by dependency upon temperature and device process variations. This causes excessive delay times in some instances, and insufficient time delays at other times, degrading digital phase detector performance. Such fixed time delays are further additionally subject to noise in part attributable to the magnitude of digital phase detector deadband.
Byrd et al. U.S. Pat. No. 4,814,726 (1989) shows a digital phase detector and a charge pump system which resets a phase comparator responsive to sourcing and sinking currents in the charge pump circuitry of the system. A reset circuit is shown which provides fixed, excessively large time delays which permit sourcing and sinking currents in a following loop filter which are subject to excessive operational deadband characteristics between sourcing and sinking operations.
Additionally, in charge pump systems using p-channel and n-channel devices responsive to input UP and DOWN signals, output signals may vary undesirably as a result of current variations in p-channel and n-channel portions of the charge pump system.